Exemplary embodiments relate to a voltage switch circuit and a nonvolatile memory device using the same and, more particularly, to a nonvolatile memory device using a voltage switch circuit which can transfer a negative voltage and a positive voltage to the word lines of a memory cell block.
There has been an increasing demand for semiconductor memory devices which can be electrically programmed and erased and yet do not require the refresh function of rewriting data at specific intervals. In manufacturing high-capacity memory devices capable of storing large data, memory devices adapted for high integration such as flash memories are useful.
Here, flash memory devices are mainly divided into NAND type flash memory devices and NOR type flash memory devices. NOR type flash memory devices have benefits such as superior random access time characteristics due to the memory cells being independently coupled to bit lines and word lines. NAND type flash memory devices have benefits such as enablement of high degree of integration where a plurality of memory cells may be coupled together in series and use only one contact for every cell string. Accordingly, NAND type flash memory is often used in high-integration nonvolatile memory devices.
With respect to NAND type flash memory devices, margins between threshold voltage distributions of memory cells may be improved by a fine control of the threshold voltage distributions including those in a negative voltage region. In order to accurately control threshold voltage distributions in the negative region, a negative voltage lower than 0 V is to be used as a verification voltage.
A NAND type flash memory device may use a block selection circuit for selecting a memory cell array on a block by block basis in order to perform the program, read, and erase operations of memory cells. However, a conventional block selection circuit may only be able to transfer a positive voltage, and not a negative voltage, to a selected memory cell array. Accordingly, the threshold voltage distributions of memory cells of the selected memory cell array are limited to a positive region. In multi-level cells having a plurality of threshold voltage distributions, such an arrangement of threshold voltage distributions reduces margins between the threshold voltage distributions.